The present invention relates to interconnection structures, including interlevel interconnection structures, devices containing these structures, and methods of making these structures and devices.
Typically, interconnection structures between conducting layers in an integrated circuit are known as contacts or vias (hereinafter “vias”), which are usually metallic structures that have ends in electrical contact with the conducting layers. The vias are typically formed by depositing a dielectric layer over a first conducting layer, etching a hole through the dielectric layer, filling the holes with a conductive material to form the vias, then etching or polishing away any excess conductor material. If the via material differs from that of the overlying conducting layer, then one typically forms the overlying conducting layer separately, on top of the vias and the dielectric material after removing the excess conductive material of the vias. The first conducting layer will be on an insulating layer (usually phosphorous silicate glass) that is itself on the active layer that contains transistors, etc.; this first conducting layer will have contacts to the transistors, etc.
Typically, contact structures are designed so that they are fully enclosed by the first conducting layer (when viewed from above). The probability that a contact feature will be fully enclosed can be calculated from the distributions of critical dimension (CD) target for the contact and the first conducting layer, and the alignment tolerance of the first conducting layer to the contact; it is assumed that any case where the metal does not fully cover the contact results in yield loss. Therefore, a relation between the drawn overlap and the alignment yield is now set. This gives the Lynch equation (I), where overlap is the Lynch value:                               overlap          =                                    σ              f                        ×                                          (                                                      B                    2                                    +                  1                                )                                            1                /                2                                      ×                                          {                                  ln                  ⁡                                      [                                                                                            (                                                      1                            -                                                          y                              a                                                                                )                                                                          -                          1                                                                    ×                                                                        (                                                                                    1                                                              B                                2                                                                                      +                            1                                                    )                                                                                                      -                            1                                                    /                          2                                                                                      ]                                                  }                                            1                /                2                                                    ,                            (        I        )            where   B  =                    n            ×              σ        m                            2            ×              (                              σ            f                    2                )                σf=std. deviation of linewidth    σm=std. deviation of misalignment    n=number of alignments    ya=alignment yield
Borderless contacts are contacts that are formed without using a structure which prevents any portion of the via from landing outside of the intended contact area. A typical borderless contact structure, formed as designed, is illustrated in FIG. 4. Shown in this figure are a phosphorous silicate glass layer 2 (which is on the semiconductor substrate), a capping oxide layer 4, titanium local interconnections 6, an interlayer dielectric oxide layer 8, and an aluminum conducting layer 16. Also shown is via 14 of tungsten and a via liner 12 of TiN, which electrically connects the conducting layer and the local interconnections. Optionally, the via may be filled with the aluminum of the conducting layer, in which case the liner may act as a seed layer.
This structure may be formed by the process illustrated in FIGS. 1–3. First, the phosphorous silicate glass layer 2 is formed, followed by forming a capping oxide layer 4, and a titanium layer. The titanium layer is patterned to form the titanium local interconnections 6, as shown in FIG. 1. Next, an interlayer dielectric oxide layer 8 is formed by low temperature (LT) chemical vapor deposition (CVD) on the substrate. This layer is planarized by chemical-mechanical polishing (CMP), and optionally, an oxide capping layer may also be applied (not illustrated), as shown in FIG. 2. A photoresist layer is then applied and patterned for the via definition, and an oxide etch is used to form the hole 10 usually with 100% overetch to remove all oxide at the bottom of the hole, and then the photoresist is removed, as shown in FIG. 3. Next, this hole is lined with TiN, typically by CVD or physical vapor deposition (PVD), to form the via liner 12, and the via filled with tungsten by CVD, followed by CMP, to complete formation of the via 14. Finally, the aluminum conducting layer 16 is formed. This aluminum based conducting layer may be patterned, and additional conducting layers, separated by dielectric layers, may be formed and patterned.
Fully enclosed contacts may suffer from disadvantages. The landing area of the via on the local interconnects should be large enough so that they are fully enclosed. This may prevent further shrinkage of the semiconductor devices, in order to accommodate the required landing area. If the via is not fully enclosed (i.e. borderless), then misalignment may result in the structure, as shown in FIG. 5. In this figure, tooth-shape region 18 may form. Since an over-etch is needed at the end of the oxide etch which forms the hole 10 (of FIG. 3), misalignment causes a continued etching well below the top of the local interconnection, forming a long narrow channel. Volatile material may remain at the bottom of this channel, causing eruptions during tungsten deposition. Furthermore, the large aspect ratio of this long narrow channel may impede tungsten deposition by CVD. If aluminum is deposited in the via rather than tungsten, a continuous seed layer may be difficult to form. The inclusion of a spacer formed of an etch-stop material on the edges of the local interconnections may help avoid these problems, but increases the cost of fabrication.